1. Field of the Invention
The present invention relates to a 0.75-power computing apparatus and method and a program for use therewith, and more particularly to a 0.75-power computing method for use in the quantization of an audio signal.
2. Description of the Related Art
Conventionally, as an audio coding method, the details of the MPEG (Moving Picture Experts Group)-2 AAC (Advanced Audio Coding) standardization that is an international standard method were described in “Information Technology—Generic coding of moving pictures and associated audio, Part 7: Advanced Audio Coding, AAC” (1997).
A configuration of an MPEG-2 AAC coding device is shown in FIG. 3. As shown in FIG. 3, the conventional audio coding device represented by this MPEG-2 AAC is typically constituted of a transform section 11 for transforming an input audio signal to generate a transformed signal, a psychoacoustic analysis section 12 for making the analysis simulating the auditory characteristic for the input audio signal to compute a quantization precision, a quantization section 13 for quantizing the transformed signal at the quantization precision, and a bit stream generating section 14 for generating a bit stream by multiplexing the transformed signal quantized at the quantization precision and the like.
The transform section 11 transforms the input audio signal to generate the transformed signal, and output it to the quantization section 13. The MPEG-2 AAC employs the MDCT (Modified Discrete Cosine Transform) as the transform. The psychoacoustic analysis section 12 makes the analysis simulating the auditory characteristic for the input audio signal to compute the quantization precision and output it to the quantization section 13.
The quantization section 13 quantizes the map signal in accordance with the quantization precision obtained by the psychoacoustic analysis section 12 to output a quantized value to the bit stream generating section 14. The bit stream generating section 14 makes the Huffman coding of the quantized value, and multiplexes it with auxiliary information required in decoding the quantization precision and the like to form the bit stream and output it.
Herein, the details of the blocks other than the quantization section 13 are described in the MPEG-2 AAC specification and so on and widely well known, and therefore the description of their blocks will be omitted.
The quantization section 13 quantizes the transformed signal M output from the transform section 11, using the quantization precision (2N) obtained by the psychoacoustic analysis section 12, in accordance with a computation expression as follows:L=INT((ABS(M)·2N)0.75+0.4054)  (1)
so that the quantized value L is obtained. Where ABS(Z) is a function that returns the absolute value of Z, and INT(Z) is a function that returns an integral part of Z by truncating the decimal fraction.
In the expression (1), the absolute value ABS(M) is firstly obtained for the transformed signal M output from the transform section 11. Then, the absolute value ABS(M) is multiplied by (2N) that is the quantization precision obtained by the psychoacoustic analysis section 12, the multiplied result is raised to the 0.75-power, and 0.4054 is added. Further, the integral part of the computed result is taken to acquire the quantized value L.
This expression (1) is executed many times in coding the audio signal, thereby requiring a large amount of arithmetical operation. Particularly, since the computation of the 0.75-power takes most part of the arithmetical operation, the efficient computation of the 0.75-power is indispensable for decreasing the amount of arithmetical operation and reducing the size of apparatus.
Conventionally, the efficient computation method of computing the 0.75-power is well known in the following two ways. A first method is shown in FIGS. 4 and 5. FIG. 4 is a block diagram showing the configuration of the conventional efficient 0.75-power computing apparatus, and FIG. 5 is a flowchart showing its computation procedure.
The conventional efficient 0.75-power computing apparatus as shown in FIG. 4 comprises first 0.5-power computing means 21, multiplication means 22, and second 0.5-power computing means 23. The first 0.5-power computing means 21 computes the 0.5-power of an input value A (step S11 in FIG. 5) and outputs its operation result B (=A0.5) to the multiplication means 22.
The multiplication means 22 calculates the product between the operation result B output from the first 0.5-power computing means 21 and the input value A (step S12 in FIG. 5), and outputs the operation result C (=A×B) to the second 0.5-power computing means 23.
The second 0.5-power computing means 23 calculates the 0.5-power of the operation result C output from the multiplication means 22 (step S13 in FIG. 5), and outputs its operation result D (=C0.5). The value of the operation result D obtained in the above manner is the 0.75-power of the input value A.
Consider the clock number (operation amount) that is required when the above method is implemented on a microprocessor element widely employed at present as a CPU (Central Processing Unit) of a personal computer. Assuming that this microprocessor element requires 29 clocks at minimum for computing the 0.5-power (SQRT instruction), and 5 clocks for the multiplication (MUL instruction), the computing procedure as shown in FIG. 5 takes (29+5+29)=63 clocks in total.
A second method with a smaller number of clocks is shown in FIGS. 6 and 7. FIG. 6 is a block diagram showing the configuration of the conventional efficient 0.75-power computing apparatus, and FIG. 7 is a flowchart showing its computing procedure.
The conventional efficient 0.75-power computing apparatus comprises first −0.5-power computing means 31, first multiplication means 32, second −0.5-power computing means 33, second multiplication means 34, and indefinite value replacing means 35, as shown in FIG. 6.
The first −0.5-power computing means 31 computes the −0.5-power of an input value A (step S21 in FIG. 7) and outputs its operation result B (=A−0.5) to the first multiplication means 32 and the second −0.5-power computing means 33. The first multiplication means 32 calculates the product between the operation result B output from the first −0.5-power computing means 31 and the input value A (step S22 in FIG. 7), and outputs the operation result C (=A×B) to the second multiplication means 34.
The second −0.5-power computing means 33 calculates the −0.5-power of the operation result B output from the first −0.5 computing means 31 (step S23 in FIG. 7), and outputs its operation result D (=B−0.5). The second multiplication means 34 calculates the product between the operation result C output from the first multiplication means 32 and the operation result D output from the second −0.5-power computing means 33 (step S24 in FIG. 7), and outputs the operation result E (=C×D). The value E obtained in the above manner is the 0.75-power of the input value A.
When the second method is implemented on the microprocessor element, assuming that this microprocessor element requires 2 clocks for computing the −0.5-power (RSQRT instruction), and 5 clocks for the multiplication (MUL instruction), the computing procedure as shown in FIG. 7 takes (2+5+2+5)=14 clocks in total. If steps S22 and S23 having no mutual dependency on the arithmetical operation can be performed in parallel at the same time, the computing procedure requires (2+5+5)=12 clocks in total.
By employing this second method, the required number of clocks (arithmetical operation amount) can be reduced from 64 clocks required in employing the first method to 12 clocks. However, the second method gives rise to the problem when the input value A is equal to zero.
In the case where the second method is implemented on the microprocessor element, because the RSQRT instruction for computing the −0.5-power makes an approximate computation, the operation result of the −0.5-power of zero (0) is a particular value indicating the infinity. Hence, the value of the operation result B at step S21 is the particular value indicating the infinity.
Moreover, because the result of multiplication between the infinity and zero (0) is an indefinite value, the value of the operation result C at step S22 is a particular value indicating an indefinite value. At step S24, since the operation result C of one multiplication is the indefinite value, the multiplication result E is also the particular value indicating the indefinite value.
Accordingly, it is necessary to perform an operation of replacing the operation result of the 0.75-power computing with zero only if the input value A is equal to zero, or an operation of replacing the operation result with zero only if the operation result is the indefinite value (indefinite value replacing means 35 in FIG. 6, steps S25 and S26 in FIG. 7). This processing needs a conditional judgement instruction, and typically takes a great number of clocks.
The conventional 0.75-power computing apparatus as shown in FIG. 6 requires the conditional judgement processing when the input value is equal to zero, and thus has a problem that the amount of arithmetical operation is increased.